Following the recent official establishment of its Chip Business Unit ("CBU"), the Company announced that its next-generation customized storage controller, designed to address the concurrent data throughput demands of AI large models, has successfully completed the initial system-level architecture specification. Concurrently, the team has preliminarily validated its core data flow algorithmic through software simulation.

The achievement of this engineering milestone signifies that the CBU, led by Vice President Mr. Siyang Hu, is efficiently translating its strategic blueprint into tangible hardware design progress, steadily advancing its goal to alleviate the underlying Input/Output ("I/O") bottlenecks of AI compute.

Addressing the AI Infrastructure Bottlenecks in the Era of Large Models

With the surging application of large language models, mixture of experts architectures, and multi-modal AI, computing infrastructure is facing structural challenges. During distributed large-scale training and inference, the overall system performance bottleneck is gradually shifting from GPU logic compute power to the read/write latency and storage bandwidth of underlying tensor data—referred to in the industry as the "Memory Wall" and "I/O Wall." Currently, AI data centers are facing the following pain points:

  • High-concurrency and fine-grained read/write demands: The training of AI large models involves massive, high-frequency concurrent read/write operations of unstructured small files, which significantly exceeds the capabilities of traditional cloud storage architectures.
  • Instruction congestion caused by traditional protocol stacks: The complex software protocol stacks and background garbage collection mechanisms of widely used general-purpose Solid State Drive controllers, based on standard block storage protocols (such as NVMe/TCP), are prone to causing instruction queue congestion when processing extreme AI task flows.
  • Tail latency reducing compute efficiency: The tail latency generated by these factors easily causes expensive advanced-node GPUs to fall into a state of "Data Starvation," thereby significantly diluting the overall effective compute utilization rate of data centers.

     

Core Technological Progress: Architecture Definition and Software Modeling

To fundamentally optimize compute efficiency, the 3 E Network CBU redesigned the storage controller architecture focusing on the underlying logic of data flow efficiency. The technological progress announced today encompasses the following phased engineering milestones:

  • Completion of the initial architecture specification: The R&D team completed a Version 1.0 system-level specification for the storage controller, setting out the preliminary engineering requirements and functional parameters for the detailed circuit design phase.
  • Development of high-speed bus and routing strategies: The specification sets out a proposed framework for supporting high-speed bus standards, including customized interface logic designed to support PCIe and CXL standards, and a preliminary routing strategy intended to reduce latency for the Memory Management Unit.
  • Software modeling of short-path data flow: Addressing the latency issues of traditional protocol stacks, the R&D team utilized high-level languages to build a system-level software simulator and successfully ran a preliminary model of a direct memory access strategy optimized for tensor data within this software environment.
  • Simulation-based optimization of I/O throughput: Early software simulation data indicates that this "short-path" algorithm model, which aims to bypass redundant protocol stacks, can potentially reduce context switching overhead. In future physical silicon implementations, this design is expected to shorten instruction queue latency, potentially optimizing the overall I/O throughput performance of compute clusters.

Management Commentary and Next Steps

Mr. Siyang Hu, Vice President and Head of the CBU at 3 E Network, stated: "In the rigorous semiconductor development process, the system architecture definition is crucial, as it sets the foundational framework for the chip’s ultimate performance. Since the department’s inception, within a short period, our team has efficiently completed the initial architecture specification for the AI storage system and preliminarily validated the software models of our core algorithms. This demonstrates the team’s solid design capabilities and execution, proving our ability to translate strategic vision into concrete engineering practice. We remain committed to addressing the underlying I/O bottleneck issues in AI compute."

Dr. Tingjun Yang, Chief Executive Officer of 3 E Network, commented: "Underlying semiconductor R&D requires long-term patience and systematic engineering planning. The progress announced today represents a steady and important step forward. It transparently demonstrates to the market that 3 E Network is strengthening its core technologies capabilities."

With the initial shaping of the system-level architectural design, the 3 E Network chip R&D team has entered a more detailed micro-architecture design phase and has begun the highly complex register transfer level front-end logic coding. The Company will continue to follow the objective laws of semiconductor R&D as it continues to progress toward subsequent engineering milestones.